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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD4235G2 датащи(PDF) 33 Page - STMicroelectronics |
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PSD4235G2 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 89 page  33/89 PSD4235G2 DECODE PLD (DPLD) The DPLD, shown in Figure 13, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: s 8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms each) s 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) s 1 internal SRAM Select (RS0) signal (three product terms) s 1 internal CSIOP Select (PSD Configuration Register) signal s 1 JTAG Select signal (enables JTAG-ISP on Port E) s 2 internal Peripheral Select signals (Peripheral I/O mode). Figure 13. DPLD Logic Array Note: 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought ino the PSD via Port A, B, C, D, or F. (INPUTS) (32) (8) (16) (1) PDN (APD OUTPUT) I /O PORTS (PORT A,B,F) (8) PGR0 - PGR7 (8) MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) A[15:0] * (4) (3) PD[3:0] (ALE,CLKIN,CSI) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (1) (1) RESET RD_BSY RS0 CSIOP PSEL0 PSEL1 8 PRIMARY FLASH MEMORY SECTOR SELECTS SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT CSBOOT 0 CSBOOT 1 CSBOOT 2 CSBOOT 3 FS0 FS7 3 3 3 3 3 3 3 3 3 3 3 3 3 JTAGSEL AI05738 FS1 FS2 FS3 FS6 FS5 FS4 1 1 1 1 |
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