PSD4235G2 datasheet(12/89 Pages) STMICROELECTRONICS

12 / 89 page

PSD4235G2

12/89

PA0-PA7

51-58

I/O

CMOS

Open

Drain

These pins make up Port A. These port pins are configurable and can have the

following functions:

1. MCU I/O – standard output or input port.

2. CPLD Macrocell (McellA0-McellA7) outputs.

3. Latched, transparent or registered PLD inputs (can also be PLD input for address

A16 and above).

PB0-PB7

61-68

I/O

CMOS

Open

Drain

These pins make up Port B. These port pins are configurable and can have the

following functions:

1. MCU I/O – standard output or input port.

2. CPLD Macrocell (McellB0-McellB7) outputs.

3. Latched, transparent or registered PLD inputs (can also be PLD input for address

A16 and above).

PC0-PC7

41-48

I/O

CMOS

Slew

Rate

These pins make up Port C. These port pins are configurable and can have the

following functions:

1. MCU I/O – standard output or input port.

2. External Chip Select (ECS0-ECS7) outputs.

3. Latched, transparent or registered PLD inputs (can also be PLD input for address

A16 and above).

PD0

I/O

CMOS

Open

Drain

PD0 pin of Port D. This port pin can be configured to have the following functions:

1. ALE/AS input – latches address on ADIO0-ADIO15.

2. AS input – latches address on ADIO0-ADIO15 on the rising edge.

3. MCU I/O – standard output or input port.

4. Transparent PLD input (can also be PLD input for address A16 and above).

PD1

I/O

CMOS

Open

Drain

PD1 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Transparent PLD input (can also be PLD input for address A16 and above).

3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,

and the CPLD AND Array.

PD2

I/O

CMOS

Open

Drain

PD2 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Transparent PLD input (can also be PLD input for address A16 and above).

3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and

I/O. When High, the PSD memory blocks are disabled to conserve power. The falling

edge of this signal can be used to get the device out of Power-down mode.

PD3

I/O

CMOS

Open

Drain

PD3 pin of Port D. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Transparent PLD input (can also be PLD input for address A16 and above).

3. WRH – for 16-bit data bus, write to high byte, active low.

PE0

I/O

CMOS

Open

Drain

PE0 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TMS Input for the JTAG Serial Interface.

PE1

I/O

CMOS

Open

Drain

PE1 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TCK Input for the JTAG Serial Interface.

PE2

I/O

CMOS

Open

Drain

PE2 pin of Port E. This port pin can be configured to have the following functions:

1. MCU I/O – standard output or input port.

2. Latched address output.

3. TDI input for the JTAG Serial Interface.

Pin Name

Type

Description

PSD4235G2 датащи(PDF) 12 Page - STMicroelectronics

PSD4235G2 датащи(HTML) 12 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

датащи скачать

ссылки URL