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PSD4235G2 датащи(PDF) 72 Page - STMicroelectronics

номер детали PSD4235G2
подробное описание детали  Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PDF  89 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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PSD4235G2 датащи(HTML) 72 Page - STMicroelectronics

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Table 61. CPLD Combinatorial Timing
Note: 1. Fast Slew Rate output available on Port C and Port F.
Table 62. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on Port C and Port F.
2. CLKIN (PD1) tCLCL = tCH + tCL .
Symbol
Parameter
Conditions
-70
-90
Fast
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
tPD
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
20
25
+ 2
+ 12
– 2
ns
tEA
CPLD Input to CPLD
Output Enable
21
26
+ 12
– 2
ns
tER
CPLD Input to CPLD
Output Disable
21
26
+ 12
– 2
ns
tARP
CPLD Register Clear
or Preset Delay
21
26
+ 12
– 2
ns
tARPW
CPLD Register Clear
or Preset Pulse Width
10
20
+ 12
ns
tARD
CPLD Array Delay
Any
Macrocell
11
16
+ 2
ns
Symbol
Parameter
Conditions
-70
-90
Fast
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
fMAX
Maximum Frequency
External Feedback
1/(tS+tCO)
34.4
30.30
MHz
Maximum Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
52.6
43.48
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
83.3
50.00
MHz
tS
Input Setup Time
14
15
+ 2
+ 12
ns
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
6
10
ns
tCL
Clock Low Time
Clock Input
6
10
ns
tCO
Clock to Output
Delay
Clock Input
15
18
– 2
ns
tARD
CPLD Array Delay
Any Macrocell
11
16
+ 2
ns
tMIN
Minimum Clock
Period 2
tCH+tCL
12
20
ns



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