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PSD4235G2 датащи(PDF) 57 Page - STMicroelectronics

номер детали PSD4235G2
подробное описание детали  Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PDF  89 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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PSD4235G2 датащи(HTML) 57 Page - STMicroelectronics

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PSD4235G2
Figure 30. Port D Structure
Port D – Functionality and Structure
Port D has four I/O pins. See Figure 30. Port D can
be configured to perform one or more of the follow-
ing functions:
s
MCU I/O mode
s
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
Port D pins can be configured in PSDsoft Ex-
press as input pins for other dedicated func-
tions:
s
Address Strobe (ALE/AS, PD0)
s
CLKIN (PD1) as input to the Macrocells Flip-
flops and APD counter
s
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
s
Write Enable High-byte (WRH, PD3) input, or as
DBE input from a MC68HC912.
Port E – Functionality and Structure
Port E can be configured to perform one or more
of the following functions (see Figure 31):
s
MCU I/O Mode
s
In-System Programming (ISP) – JTAG port can
be enabled for programming/erase of the PSD
device. (See the section entitled “Reset
(RESET) Timing”, on page 63, for more
information on JTAG programming.)
s
Open Drain – pins can be configured in Open
Drain Mode
s
Battery Backup features
– PE6 can be configured for a battery input sup-
ply, Voltage Stand-by (VSTBY).
– PE7 can be configured as a Battery-on Indi-
cator (VBATON), indicating when VCC is less
than VBAT.
s
Latched Address output – Provide latched
address output.
DATA OUT
Register
DQ
DQ
WR
WR
READ MUX
P
D
B
CPLD - INPUT
DIR Register
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI04937



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