PSD4235G2 datasheet(63/89 Pages) STMICROELECTRONICS

63 / 89 page

63/89

PSD4235G2

Figure 34. Reset (RESET) Timing

Programming In-Circuit using the JTAG Serial

Interface

The JTAG Serial Interface on the PSD can be en-

abled on Port E (see Table 52). All memory blocks

(primary Flash memory and secondary Flash

memory), PLD logic, and PSD Configuration bits

may be programmed through the JTAG-ISC Serial

Interface. A blank device can be mounted on a

printed circuit board and programmed using JTAG

In-System Programming (ISP).

The standard JTAG signals (IEEE 1149.1) are

TMS, TCK, TDI, and TDO. Two additional signals,

TSTAT and TERR, are optional JTAG extensions

used to speed up Program and Erase cycles.

By default, on a blank PSD (as shipped from the

factory, or after erasure), four pins on Port E are

enabled for the basic JTAG signals TMS, TCK,

TDI, and TDO.

See Application Note

AN1153 for more details on

JTAG In-System Programming (ISP).

Standard JTAG Signals. The

standard

JTAG

signals (TMS, TCK, TDI, and TDO) can be en-

abled by any of three different conditions that are

logically ORed. When enabled, TDI, TDO, TCK,

and TMS are inputs, waiting for a serial command

from an external JTAG controller device (such as

FlashLINK or Automated Test Equipment). When

the enabling command is received from the exter-

nal JTAG controller device, TDO becomes an out-

put and the JTAG channel is fully functional inside

the PSD. The same command that enables the

JTAG channel may optionally enable the two addi-

tional JTAG pins, TSTAT and TERR.

The following symbolic logic equation specifies the

conditions enabling the four basic JTAG pins

(TMS, TCK, TDI, and TDO) on their respective

Port E pins. For purposes of discussion, the logic

label JTAG_ON is used. When JTAG_ON is true,

the four pins are enabled for JTAG. When

JTAG_ON is false, the four pins can be used for

general PSD I/O.

JTAG_ON = PSDsoft Express_enabled +

/* An NVM configuration bit inside the

PSD

set

the

designer

the

PSDsoft Express Configuration utility.

This dedicates the pins for JTAG at all

times (compliant with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a bit at

run-time

writing

the

PSD

JTAG

Enable.

This

located

address

CSIOP

offset

C7h.

Setting

the

JTAG_ENABLE

bit

this register will enable the pins for

JTAG use. This bit is cleared by a PSD

reset

the

microcontroller.

See

Table 21 for bit definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT) inside

the PSD can be used to enable the JTAG

pins.

This

has

the

reserved

name

JTAGSEL.

Once

defined

node

PSDabel,

the

designer

can

write

equation

for

JTAGSEL.

This

method

used

when

the

Port

JTAG

pins

are

multiplexed with other I/O signals. It

recommended

tie

logically

the

node JTAGSEL to the JEN\ signal on the

Flashlink cable when multiplexing JTAG

signals. See Application Note 1153 for

details. */

The state of the PSD Reset (RESET) signal does

not interrupt (or prevent) JTAG operations if the

JTAG pins are dedicated by an NVM configuration

bit (via PSDsoft Express). However, Reset (RE-

SET) will prevent or interrupt JTAG operations if

the JTAG Enable Register (as shown in Table 21)

is used to enable the JTAG pins.

The PSD supports JTAG In-System-Programma-

bility (ISP) commands, but not Boundary Scan.

ST’s

PSDsoft

Express

software

tool

and

FlashLINK JTAG programming cable implement

the JTAG In-System-Programmability (ISP) com-

mands.

Table 52. JTAG Port Signals

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

Port E Pin

JTAG Signals

Description

PE0

TMS

Mode Select

PE1

TCK

Clock

PE2

TDI

Serial Data In

PE3

TDO

Serial Data Out

PSD4235G2 датащи(PDF) 63 Page - STMicroelectronics

PSD4235G2 датащи(HTML) 63 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

датащи скачать

ссылки URL