PSD4235G2 datasheet(54/89 Pages) STMICROELECTRONICS

54 / 89 page

PSD4235G2

54/89

Figure 28. Peripheral I/O Mode

Direction Register. The Direction Register con-

trols the direction of data flow in the I/O Ports. Any

bit set to 1 in the Direction Register causes the

corresponding pin to be an output, and any bit set

to 0 causes it to be an input. The default mode for

all port pins is input.

Table 43. Port Pin Direction Control, Output

Enable P.T. Not Defined

Table 44. Port Pin Direction Control, Output

Enable P.T. Defined

Table 45. Port Direction Assignment Example

Figure 29 and Figure 31 show the Port Architec-

ture diagrams for Ports A/B/C and E/F/G, respec-

tively. The direction of data flow for Ports A, B, C

and F are controlled not only by the direction reg-

ister, but also by the output enable product term

from the PLD AND Array. If the output enable

product term is not active, the Direction Register

has sole control of a given pin’s direction.

An example of a configuration for a Port with the

three least significant bits set to output and the re-

mainder set to input is shown in Table 45. Since

Port D only contains four pins, the Direction Reg-

ister for Port D has only the four least significant

bits active.

Drive Select Register. The Drive Select Register

configures the pin driver as Open Drain or CMOS

for some port pins, and controls the slew rate for

the other port pins. An external pull-up resistor

should be used for pins configured as Open Drain.

A pin can be configured as Open Drain if its corre-

sponding bit in the Drive Select Register is set to a

1. The default pin drive is CMOS.

(The slew rate is a measurement of the rise and

fall times of an output. A higher slew rate means a

faster output response and may create more elec-

trical noise. A pin operates in a high slew rate

when the corresponding bit in the Drive Register is

set to 1. The default rate is slow slew.)

Table 46 shows the Drive Register for Ports A, B,

C, D, E, F and G. It summarizes which pins can be

configured as Open Drain outputs and which pins

the slew rate can be set for.

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PA0 - PA7

D0-D7

DATA BUS

AI02886

Direction Register Bit

Port Pin Mode

Input

Output

Direction

Output Enable

P.T.

Port Pin Mode

Input

Output

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PSD4235G2 датащи(PDF) 54 Page - STMicroelectronics

PSD4235G2 датащи(HTML) 54 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

датащи скачать

ссылки URL