PSD4235G2 datasheet(26/89 Pages) STMICROELECTRONICS

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PSD4235G2

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reads this location until the embedded algorithm is

complete. The MCU continues to read this loca-

tion, checking the Toggle Flag (DQ6/DQ14) bit

and monitoring the Error Flag (DQ5/DQ13) bit.

When the Toggle Flag (DQ6/DQ14) bit stops tog-

gling (two consecutive reads yield the same val-

ue), and the Error Flag (DQ5/DQ13) bit remains 0,

the embedded algorithm is complete. If the Error

Flag (DQ5/DQ13) bit is 1, the MCU should test the

Toggle Flag (DQ6/DQ14) bit again, since the Tog-

gle Flag (DQ6/DQ14) bit may have changed simul-

taneously with the Error Flag (DQ5/DQ13) bit (see

Figure 7).

Figure 7. Data Toggle Flowchart

The Error Flag (DQ5/DQ13) bit is set if either an in-

ternal time-out occurred while the embedded algo-

rithm attempted to program, or if the MCU

attempted to program a 1 to a bit that was not

erased (not erased is logic 0).

It is suggested (as with all Flash memories) to read

the location again after the embedded program-

ming algorithm has completed, to compare the

word that was written to Flash memory with the

word that was intended to be written.

When using the Data Toggle method after an

Erase cycle, Figure 7 still applies. the Toggle Flag

(DQ6/DQ14) bit toggles until the Erase cycle is

complete. A 1 on the Error Flag (DQ5/DQ13) bit in-

dicates a time-out condition on the Erase cycle, a

0 indicates no error. The MCU can read any even

location within the sector being erased to get the

Toggle Flag (DQ6/DQ14) bit and the Error Flag

(DQ5/DQ13) bit.

PSDsoft Express generates ANSI C code func-

tions which implement these Data Toggling algo-

rithms.

Unlock Bypass. The Unlock Bypass instruction

allows the system to program words to the Flash

memories faster than using the standard Program

instruction. The Unlock Bypass mode is entered

by first initiating two Unlock cycles. This is followed

by a third Write cycle containing the Unlock By-

pass command, 20h (as shown in Table 29). The

Flash memory then enters the Unlock Bypass

mode.

A two-cycle Unlock Bypass Program instruction is

all that is required to program in this mode. The

first cycle in this instruction contains the Unlock

Bypass Program command, A0h. The second cy-

cle contains the program address and data. Addi-

tional data is programmed in the same manner.

This mode dispense with the initial two Unlock cy-

cles required in the standard Program instruction,

resulting in faster total programming time.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset in-

structions are valid.

To exit the Unlock Bypass mode, the system must

issue the two-cycle Unlock Bypass Reset instruc-

tion. The first cycle must contain the data 90h; the

second cycle the data 00h. Addresses are Don’t

Care for both cycles. The Flash memory then re-

turns to Read mode.

Erasing Flash Memory

Flash Bulk Erase. The Flash Bulk Erase instruc-

tion uses six Write operations followed by a Read

operation of the status register, as described in

Table 29. If any byte of the Bulk Erase instruction

is wrong, the Bulk Erase instruction aborts and the

device is reset to the Read Memory mode.

During a Bulk Erase, the memory status may be

checked by reading the Error Flag (DQ5/DQ13)

bit, the Toggle Flag (DQ6/DQ14) bit, and the Data

Polling (DQ7/DQ15) bit, as detailed in the section

START

READ DQ6

(DQ14)

AI04921

Yes

Program

or Erase

Cycle failed

Program

or Erase

Cycle is

complete

Issue RESET

instruction

READ DQ5 and DQ6

(DQ13 and DQ14)

at Valid Even Address

DQ5

(DQ13)

= 1

DQ6

(DQ14)

Toggle

DQ6

(DQ14)

Toggle

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