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PSD4235G2 датащи(PDF) 25 Page - STMicroelectronics |
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PSD4235G2 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 89 page ![]() 25/89 PSD4235G2 Sector Erase cycle for a period of 100 µs + 20% unless an additional Sector Erase instruction is de- coded. After this period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag (DQ3/DQ11) bit is set to 1. Programming Flash Memory Flash memory must be erased prior to being pro- grammed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash mem- ory occurs on a sector or device basis, program- ming Flash memory occurs on a word basis. The primary and secondary Flash memories re- quire the MCU to send an instruction to program a word or to erase sectors (see Table 29). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are in- voked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal. Data Polling. Polling on the Data Polling (DQ7/ DQ15) bit is a method of checking whether a Pro- gram or Erase cycle is in progress or has complet- ed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be pro- grammed in Flash memory to check the status. The Data Polling (DQ7/DQ15) bit becomes the complement of the corresponding bit of the original data word to be programmed. The MCU continues to poll this location, comparing data and monitor- ing the Error Flag (DQ5/DQ13) bit. When the Data Polling (DQ7/DQ15) bit matches the correspond- ing bit of the original data, and the Error Flag (DQ5/DQ13) bit remains 0, the embedded algo- rithm is complete. If the Error Flag (DQ5/DQ13) bit is 1, the MCU should test the Data Polling (DQ7/ DQ15) bit again since the Data Polling (DQ7/ DQ15) bit may have changed simultaneously with the Error Flag (DQ5/DQ13) bit (see Figure 6). The Error Flag (DQ5/DQ13) bit is set if either an in- ternal time-out occurred while the embedded algo- rithm attempted to program the location or if the MCU attempted to program a 1 to a bit that was not erased (not erased is logic 0). It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling (DQ7/DQ15) bit is 0 until the Erase cycle is complete. A 1 on the Error Flag (DQ5/ DQ13) bit indicates a time-out condition on the Erase cycle, a 0 indicates no error. The MCU can read any even location within the sector being erased to get the Data Polling (DQ7/DQ15) bit and the Error Flag (DQ5/DQ13) bit. PSDsoft Express generates ANSI C code func- tions that implement these Data Polling algo- rithms. Figure 6. Data Polling Flowchart Data Toggle. Checking the Toggle Flag (DQ6/ DQ14) bit is another method of determining wheth- er a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algo- rithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag (DQ6/DQ14) bit toggles each time the MCU READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address START READ DQ7 (DQ15) Program or Erase Cycle failed Program or Erase Cycle is complete AI04920 Yes No Yes No DQ5 (DQ13) = 1 DQ7 (DQ15) = Data7 (Data15) Yes No Issue RESET instruction DQ7 (DQ15) = Data7 (Data15) |
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