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TMS320DM643 датащи(PDF) 117 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 117 Page - Texas Instruments |
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117 / 162 page ![]() www.ti.com 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 HAS HCNTL[1:0] HR/W HHWIL HSTROBE(A) HCS HD[15:0] (output) HRDY 3 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. HAS(A) HCNTL[1:0] HR/W HHWIL HSTROBE(B) HCS HD[15:0] (output) HRDY 1st half-word 2nd half-word 8 6 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 A. For correct operation, strobe the HAS signal only once per HSTROBE active cycle. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007 Figure 5-40. HPI16 Read Timing (HAS Not Used, Tied High) Figure 5-41. HPI16 Read Timing (HAS Used) Submit Documentation Feedback DM643 Peripheral Information and Electrical Specifications 117 |
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