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5.11.2

Host-Port Interface (HPI) Electrical Data/Timing

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

Table 5-38. Timing Requirements for Host-Port Interface Cycles

(1) (2) (see Figure 5-40 through Figure 5-47)

–500

–600

NO.

UNIT

MIN

MAX

tsu(SELV-HSTBL)

Setup time, select signals(3) valid before HSTROBE low

th(HSTBL-SELV)

Hold time, select signals(3) valid after HSTROBE low

2.4

tw(HSTBL)

Pulse duration, HSTROBE low

4P(4)

tw(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

tsu(SELV-HASL)

Setup time, select signals(3) valid before HAS low

th(HASL-SELV)

Hold time, select signals(3) valid after HAS low

tsu(HDV-HSTBH)

Setup time, host data valid before HSTROBE high

th(HSTBH-HDV)

Hold time, host data valid after HSTROBE high

2.8

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated

th(HRDYL-HSTBL)

until HRDY is active (low); otherwise, HPI writes will not complete properly.

tsu(HASL-HSTBL)

Setup time, HAS low before HSTROBE low

th(HSTBL-HASL)

Hold time, HAS low after HSTROBE low

2.1

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(3)

Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

(4)

Select the parameter value of 4P or 12.5 ns, whichever is larger.

Table 5-39. Switching Characteristics Over Recommended Operating Conditions During Host-Port

Interface Cycles

(1) (2) (see Figure 5-40 through Figure 5-47)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high(3)

1.3

4P + 8

td(HSTBL-HDLZ)

Delay time, HSTROBE low to HD low impedance for an HPI read

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

–3

toh(HSTBH-HDV)

Output hold time, HD valid after HSTROBE high

1.5

td(HSTBH-HDHZ)

Delay time, HSTROBE high to HD high impedance

td(HSTBL-HDV)

Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)

4P + 8

(1)

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(3)

This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word

transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and

HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes

high if the internal write buffer is full.

DM643 Peripheral Information and Electrical Specifications

116

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