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5.4 Enhanced Direct Memory Access (EDMA) Controller

5.4.1

EDMA Device-Specific Information

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and

the device peripherals on the DM643 DSP. These data transfers include cache servicing, non-cacheable

memory accesses, user-programmed data transfers, and host accesses.

5.4.1.1

EDMA Channel Synchronization Events

The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external

memory. Table 5-3 lists the source of C64x EDMA synchronization events associated with each of the

programmable EDMA channels. For the DM643 device, the association of an event to a channel is fixed;

each of the EDMA channels has one specific event associated with it. These specific events are captured

in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable

registers (EERL, EERH). The priority of each event can be specified independently in the transfer

parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and

how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the

TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature

number SPRU234).

Table 5-3. TMS320DM643 EDMA Channel Synchronization Events(1)

EDMA

EVENT NAME

EVENT DESCRIPTION

CHANNEL(1)

DSP_INT

HPI-to-DSP interrupt

TINT0

Timer 0 interrupt

TINT1

Timer 1 interrupt

SD_INTA

EMIFA SDRAM timer interrupt

GPINT4/EXT_INT4

GP0 event 4/External interrupt pin 4

GPINT5/EXT_INT5

GP0 event 5/External interrupt pin 5

GPINT6/EXT_INT6

GP0 event 6/External interrupt pin 6

GPINT7/EXT_INT7

GP0 event 7/External interrupt pin 7

GPINT0

GP0 event 0

GPINT1

GP0 event 1

GPINT2

GP0 event 2

GPINT3

GP0 event 3

XEVT0

McBSP0 transmit event

REVT0

McBSP0 receive event

14–18

–

None

TINT2

Timer 2 interrupt

20–31

–

None

AXEVTE0

McASP0 transmit even event

AXEVTO0

McASP0 transmit odd event

AXEVT0

McASP0 transmit event

AREVTE0

McASP0 receive even event

AREVTO0

McASP0 receive odd event

AREVT0

McASP0 receive event

VP1EVTYB

VP1 Channel B Y event DMA request

VP1EVTUB

VP1 Channel B Cb event DMA request

VP1EVTVB

VP1 Channel B Cr event DMA request

(1)

In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced

Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).

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DM643 Peripheral Information and Electrical Specifications

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