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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM643 датащи(PDF) 68 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 68 Page - Texas Instruments |
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68 / 162 page  www.ti.com 5.3.4 Peripheral Power-Down Operation 5.3.5 Power-Down Modes Logic PWRD Internal Clock Tree CPU IFR IER CSR PD1 PD2 Power- Down Logic Clock PLL CLKIN RESET CLKOUT6 PD3 Internal Peripherals CLKOUT4 Clock and Dividers Distribution TMS320DM643 A. External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic. TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007 The DM643 device can be powered down in three ways: • Power-down due to pin configuration • Power-down due to software configuration – relates to the default state of the peripheral configuration bits in the PERCFG register. • Power-down during run-time via software configuration On the DM643 device, the HPI and EMAC and MDIO peripherals are controlled (selected) at the pin level during chip reset (e.g., HD5 and MAC_EN pins). The McASP0, McBSP0, VP1, VP2, and I2C0 peripheral functions are selected via the peripheral configuration (PERCFG) register bits. For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document. Figure 5-8 shows the power-down mode logic on the DM643. Figure 5-8. Power-Down Mode Logic(A) 68 DM643 Peripheral Information and Electrical Specifications Submit Documentation Feedback |
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