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TMS320DM643 датащи(PDF) 96 Page - Texas Instruments

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номер детали TMS320DM643
подробное описание детали  Video/Imaging Fixed-Point Digital Signal Processor
PDF  162 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320DM643 датащи(HTML) 96 Page - Texas Instruments

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AECLKOUTx
ACEx
ABE[7:0]
AEA[12:3]
AED[63:0]
AAOE/ASDRAS/ASOE(A)
AARE/ASDCAS/ASADS/ASRE(A)
AAWE/ASDWE/ASWE(A)
AEA13
AEA[22:14]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
APDT(B)
14
14
A.
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
B.
APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write,
data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to
the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting
PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in this figure.
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007
Figure 5-25. SDRAM Write Command for EMIFA
DM643 Peripheral Information and Electrical Specifications
96
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