TMS320DM643 datasheet(6/162 Pages) TI

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Device Overview

2.1 Device Characteristics

2.2 CPU (DSP Core) Description

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

Table 2-1 provides an overview of the DM643 DSP. The table shows significant features of the DM643

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type

with pin count.

Table 2-1. Characteristics of the DM643 Processor

HARDWARE FEATURES

DM643

EMIFA (64-bit bus width)

(clock source = AECLKIN)

EDMA (64 independent channels)

McASP0 (uses Peripheral Clock [AUXCLK])

I2C0 (uses Peripheral Clock)

Peripherals

HPI (32- or 16-bit user selectable)

1 (HPI16 or HPI32)

McBSP

Not all peripherals pins are

(internal clock source = CPU/4 clock frequency)

available at the same time

(For more detail, see the

Configurable Video Ports (VP1 and VP2)

Device Configuration

10/100 Ethernet MAC (EMAC)

section).

Management Data Input/Output (MDIO)

VCXO Interpolated Control Port (VIC)

32-Bit Timers

(internal clock source = CPU/8 clock frequency)

General-Purpose Input/Output Port (GP0)

Size (Bytes)

288K

16K-Byte (16KB) L1 Program (L1P) Cache

On-Chip Memory

Organization

16KB L1 Data (L1D) Cache

256KB Unified Mapped RAM/Cache (L2)

CPU ID + CPU Rev ID

Control Status Register (CSR.[31:16])

0x0C01

JTAG BSDL_ID

JTAGID register (address location: 0x01B3F008)

0x0007902F

Frequency

MHz

500, 600

2 ns (DM643-500)

[500 MHz CPU, 100 MHz EMIF(1)]

Cycle Time

1.67 ns (DM643-600)

[600 MHz CPU, 133 MHz EMIF(1)]

1.2 V (-500)

Core (V)

1.4 V (-600)

Voltage

I/O (V)

3.3 V

PLL Options

CLKIN frequency multiplier

Bypass (x1), x6, x12

23 x 23 mm

548-Pin BGA (GDK and ZDK)

BGA Package

27 x 27 mm

548-Pin BGA (GNZ and ZNZ)

Process Technology

µm

0.13 µm

Product Preview (PP), Advance Information (AI),

Product Status(2)

or Production Data (PD)

(1)

On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the

EMIF device speed portion of this data sheet.

(2)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to

eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW

architecture features controls by which all eight units do not have to be supplied with instructions if they

Device Overview

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