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5.3.6

Triggering, Wake-up, and Effects

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits

15–10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 5-9 and

described in Table 5-2. When writing to the CSR, all bits of the PWRD field should be set at the same

time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is

discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number

SPRU189).

(See NOTE)

Enable or

Enabled

Reserved

Non-Enabled

PD3

PD2

PD1

(See NOTE)

Interrupt Wake

R/W-0

(See NOTE)

Legend: R/W = Readable/Writable, -n = value after reset, -x = undefined value after reset

NOTE: The shaded bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 5-9. PWRD Field of the CSR Register

A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR

before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in

the CSR to account for this delay.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction

where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will

be executed first, then the program execution returns to the instruction where PD1 took effect. In the case

with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER)

must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the

instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 5-2 summarizes all the power-down

modes.

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