TMS320DM643 datasheet(85/162 Pages) TI

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AECLKIN

AECLKOUT1

AECLKIN

AECLKOUT2

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

Table 5-18. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the

EMIFA Module

(1) (2) (3) (see Figure 5-17)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

tw(EKO1H)

Pulse duration, AECLKOUT1 high

EH – 0.7

EH + 0.7

tw(EKO1L)

Pulse duration, AECLKOUT1 low

EL – 0.7

EL + 0.7

tt(EKO1)

Transition time, AECLKOUT1

td(EKIH-EKO1H)

Delay time, AECLKIN high to AECLKOUT1 high

td(EKIL-EKO1L)

Delay time, AECLKIN low to AECLKOUT1 low

(1)

E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(2)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(3)

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

Figure 5-17. AECLKOUT1 Timing for the EMIFA Module

Table 5-19. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the

EMIFA Module

(1) (2) (see Figure 5-18)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

tw(EKO2H)

Pulse duration, AECLKOUT2 high

0.5NE – 0.7

0.5NE + 0.7

tw(EKO2L)

Pulse duration, AECLKOUT2 low

0.5NE – 0.7

0.5NE + 0.7

tt(EKO2)

Transition time, AECLKOUT2

td(EKIH-EKO2H)

Delay time, AECLKIN high to AECLKOUT2 high

td(EKIL-EKO2L)

Delay time, AECLKIN low to AECLKOUT2 low

(1)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(2)

E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. N = the EMIF input clock divider; N = 1, 2,

or 4.

Figure 5-18. AECLKOUT2 Timing for the EMIFA Module

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DM643 Peripheral Information and Electrical Specifications

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