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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320DM643 датащи(PDF) 82 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 82 Page - Texas Instruments |
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82 / 162 page  www.ti.com 5.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks) TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007 Table 5-12. TMS320DM643 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time (1) (2) GDK and ZDK PACKAGES – 23 x 23 mm BGA, GNZ and ZNZ PACKAGES – 27 x 27 mm BGA CLKMODE CLKIN CPU CLOCK TYPICAL CLKOUT4 CLKOUT6 CLKMODE1 CLKMODE0 (PLL MULTIPLY RANGE FREQUENCY LOCK TIME RANGE (MHz) RANGE (MHz) FACTORS) (MHz) RANGE (MHz) (µs)(3) 0 0 Bypass (x1) 30–75 30–75 7.5–18.8 5–12.5 N/A 0 1 x6 30–75 180–450 45–112.5 30–75 75 1 0 x12 30–50 360–600 90–150 60–100 1 1 Reserved – – – – – (1) These clock frequency range values are applicable to a DM643-600 speed device. For -500 device speed values, see the CLKIN timing requirements table for the specific device speed. (2) Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM643 device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). (3) Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. Table 5-13. Timing Requirements for CLKIN for –500 Devices (1) (2) (3) (see Figure 5-13) –500 NO. PLL MODE x12 PLL MODE x6 x1 (Bypass) UNIT MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 24 33.3 13.3 33.3 13.3 33.3 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns (1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. (3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. Table 5-14. Timing Requirements for CLKIN for –600 Devices (1) (2) (3) (see Figure 5-13) –600 NO. PLL MODE x12 PLL MODE x6 x1 (Bypass) UNIT MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 20 33.3 13.3 33.3 13.3 33.3 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.45C 0.45C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.45C 0.45C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 1 ns 5 tJ(CLKIN) Period jitter, CLKIN 0.02C 0.02C 0.02C ns (1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. (2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. (3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns. DM643 Peripheral Information and Electrical Specifications 82 Submit Documentation Feedback |
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