STM32H533CE datasheet(163/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

163/231

STM32H533xx

Electrical characteristics

200

Table 84. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FCLK

OCTOSPI clock

frequency

1.71 V < VDD < 3.6 V,

CL = 15 pF

100(4)

MHz

2.7 V < VDD < 3.6 V,

CL = 15 pF

125(4)

tw(CLKH) OCTOSPI clock

high and low time

PRESCALER[7:0] = n

(= 0, 1, 3, 5, ..255)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKL)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKH)

OCTOSPI clock

high and low time

PRESCALER[7:0] = n

(= 2, 4, 6, 8, ...254)

(n/2) * t(CLK)/

(n + 1) - 0.5

(n/2) * t(CLK)/

(n + 1) + 0.5

tw(CLKL)

(n/2 + 1) * t(CLK)/

(n + 1) - 0.5

(n/2 + 1) * t(CLK)/

(n + 1) + 0.5

tsr(IN),

tsf(IN)

Data input setup time

thr(IN),

thf(IN)

Data input hold time

1.5

tvr(OUT)

tvf(OUT)

Data output valid time

DHQC = 0

2.5

3.5

DHQC = 1,

Prescaler [7:0] = 1, 2...

t(CLK)/4 +

0.5

t(CLK)/4 + 1

thr(OUT)

thf(OUT)

Data output hold time

DHQC = 0

1.5

DHQC = 1,

Prescaler [7:0] = 1, 2...

t(CLK)/4 - 1

1. All values apply to Octal and Quad-SPI mode.

2. Evaluated by characterization - Not tested in production.

3. Delay block bypassed.

4. DHQC must be set to reach the mentioned frequency.

Table 85. OCTOSPI characteristics in DTR mode (with DQS) / hyperbus(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FCLK

OCTOSPI clock frequency

1.71 V < VDD < 3.6 V,

CL = 15 pF

125(3)(4)

MHz

2.7 V < VDD < 3.6 V,

CL = 15 pF

125(3)(5)

tw(CLKH) OCTOSPI clock

high and low time

PRESCALER[7:0] = n

= (0, 1, 3, 5, ..255)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKL)

t(CLK)/2 - 0.5

t(CLK)/2 + 0.5

tw(CLKH)

OCTOSPI clock

high and low time

PRESCALER[7:0] = n

= (2, 4, 6, 8, ...254)

(n/2)*t(CLK)/

(n+1) - 0.5

(n/2)*t(CLK)/

(n+1) + 0.5

tw(CLKL)

(n/2+1)*t(CLK)/

(n+1) - 0.5

(n/2+1)*t(CLK)/

(n+1) + 0.5

tv(CLK)

Clock valid time

t(CLK) + 2

th(CLK) Clock hold time

t(CLK)/2 - 1

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