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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H533CE датащи(PDF) 162 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 162 Page - STMicroelectronics |
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162 / 231 page  Electrical characteristics STM32H533xx 162/231 DS14539 Rev 1 5.3.18 Octo-SPI interface characteristics Unless otherwise specified, the parameters given in Table 83 and Table 84 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 20, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5 VDD • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Refer to Section 5.3.14 for more details on the input/output alternate function characteristics. Figure 33. OCTOSPI SDR read/write timing diagram Table 83. OCTOSPI characteristics in SDR mode(1)(2)(3) Symbol Parameter Conditions Min Typ Max Unit F(CLK) OCTOSPI clock frequency 1.71 V < VDD < 3.6 V, CL = 15 pF -- 110 MHz 2.7 V < VDD < 3.6 V, CL =15 pF - - 150 tw(CLKH) OCTOSPI clock high and low time, even division PRESCALER[7:0] = n (= 0, 1, 3, 5,...,255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 ns tw(CLKL) t(CLK)/2 - 0.5 - t(CK)/2 + 0.5 tw(CLKH) OCTOSPI clock high and low time, odd division PRESCALER[7:0] = n (= 2, 4, 6, ...,254) (n/2) * t(CLK) / (n + 1) - 0.5 - (n/2) * t(CLK)/ (n + 1) + 0.5 tw(CLKL) (n/2 + 1) * t(CLK)/ (n + 1) - 0.5 - (n/2 + 1) * t(CLK)/ (n + 1) + 0.5 ts(IN) Data input setup time - 4 - - th(IN) Data input hold time - 1 - - tv(OUT) Data output valid time - - 0.5 1 th(OUT) Data output hold time - 0 - - 1. All values apply to Octal and Quad-SPI mode. 2. Evaluated by characterization - Not tested in production. 3. Delay block bypassed. MSv36878V3 Data output D0 D1 D2 Clock Data input D0 D1 D2 t(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) ts(IN) th(IN) tv(OUT) th(OUT) |
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