STM32H533CE datasheet(145/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

145/231

STM32H533xx

Electrical characteristics

200

Figure 21. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 57, otherwise the reset is not taken into account by the device.

5.3.16

Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length to ensure its detection by the

event controller.

5.3.17

FMC characteristics

Unless otherwise specified, the parameters given in tables 69 to 82 are derived from tests

performed under the ambient temperature, fHCLK frequency and VDD supply voltage

conditions summarized in Table 20, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5 VDD

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

Table 67. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RPU(2)

Weak pull-up equivalent resistor(1)

1. The pull-up is designed with a true resistance in series with a switchable PMOS. The PMOS contribution to

the series resistance is minimum (~10 % order)

VIN = VSS

kΩ

VF(NRST)(2)

2. Specified by design - Not tested in production.

NRST input filtered pulse

1.71 V < VDD < 3.6 V

VNF(NRST)(2) NRST input not filtered pulse

1.71 V < VDD < 3.6 V 350

ai14132d

STM32

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit (1)

Table 68. EXTI input characteristics(1)

Specified by design - Not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PLEC

Pulse length to event controller

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