ADS5400IPZP datasheet(11/58 Pages) TI2

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ADS5400

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SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Timing Requirements (continued)

Typical values at TA = 25°C, Minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,

sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock

(unless otherwise noted)

(1).

MIN

NOM MAX

UNIT

CLKOUT edge to Data invalid, 50% CLKIN duty

(tCLK/2) -

tH-SBM

Hold time, single bus mode

410p

cycle

65p

tCLK -

tSU-DBM

Setup time, dual bus mode

Data valid to CLKOUT edge, 50% CLKIN duty cycle

550p

425p

CLKOUT edge to Data invalid, 50% CLKIN duty

tCLK +

tH-DBM

Hold time, dual bus mode

1150p

cycle

175p

LVDS rise time

Measured 20% to 80%

400

LVDS output fall time

Measured 20% to 80%

400

LVDS INPUT TIMING (RESETIN)

tRSU

RESET setup time

RESETP going HIGH to CLKINP going LOW

300

tRH

RESET hold time

CLKINP going LOW to RESETP going LOW

300

RESET input capacitance

Differential

RESET input current

±1

µA

SERIAL INTERFACE TIMING

tS-SDENB

Setup time, serial enable

SDENB falling to SCLK rising

tH-SDENB

Hold time, serial enable

SCLK falling to SENDB rising

tS-SDIO

Setup time, SDIO

SDIO valid to SCLK rising

tH-SDIO

Hold time, SDIO

SCLK rising to SDIO transition

fSCLK

Frequency

MHz

tSCLK

SCLK period

100

tSCLKH

Minimum SCLK high time

tSCLKL

Minimum SCLK low time

Rise time

10 pF

Fall time

10 pF

Data output (SDO/SDIO) delay after SCLK falling,

tDDATA

Data output delay

10-pF load

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