ADS5400IPZP datasheet(30/58 Pages) TI2

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SDENB

SCLK

SDIO

SDO

SDENB

SCLK

SDIO

SDO

InstructionCycle

DataTransferCycle(s)

r/w

3pinConfigurationOutput

4pinConfigurationOutput

Datan

Datan-1

t (Data)

InstructionCycle

DataTransferCycle(s)

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO

r/w

t (SDENB)

tSCLK

t (SDIO)

tSCLKH

tSCLKL

ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

www.ti.com

Figure 35 shows the serial interface timing diagram for a ADS5400 write operation. SCLK is the serial interface

clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in.

Input data to ADS5400 is clocked on the rising edges of SCLK.

Figure 35. Serial Interface Write Timing Diagram

Figure 36 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface

clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in

during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer

cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during

the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK

until the rising edge of SDENB when it will 3-state.

Figure 36. Serial Interface Read Timing Diagram

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