ADS5400IPZP datasheet(27/58 Pages) TI2

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Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G016

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 601.13 MHz

fIN = 100.33 MHz

fIN = 901.13 MHz

Clock Common Mode − V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

G017

fS = 1 GSPS

fIN = 1498.5 MHz

fIN = 901.13 MHz

fIN = 100.33 MHz

fIN = 601.13 MHz

ADS5400

www.ti.com

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Figure 33. ADS5400 SFDR vs Clock Common Mode

Figure 34. ADS5400 SNR vs Clock Common Mode

7.3.5 Over Range

The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This

flag is provided as an indicator that the analog input signal exceeded the full-scale input limit set in register 0x00

and 0x01 (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input

signal within acceptable limits. The OVR pins are not available when the sychronization mode is enabled, as they

become the SYNCOUT indicator.

7.3.6 Data Scramble

In normal operation, with this mode disabled, the MSBs have similar energy to the analog input fundamental

frequency and can in some instances cause board interference. A data scramble mode is available in register

0x06. In this mode, bits 11-1 are XOR'd with bit 0 (the LSB). Because of the random nature of the LSB, this has

the effect of randomizing the data pattern. To de-scramble, perform the opposite operation in the digital chip after

receiving the scrambled data.

7.3.7 Test Patterns

Determining the closure of timing or validating the digital interface can be difficult in normal operation. Therefore,

test patterns are available in register 0x06. One pattern toggles the outputs between all 1s and all 0s. Another

pattern generates a 7-bit PRBS (pseudo-random bit sequence).

In dual bus mode, the toggle mode could be in the same phase on bus A and B (bus A and B outputting 1s or 0s

together), or could be out of phase (bus A outputting 1s while bus B outputs 0s). The start phase cannot be

controlled.

The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedback shift register

where the two last bits of the shift register are exclusive-OR’ed and fed back to the first bit of the shift register.

The standard notation for the polynomial is x7 + x6 + 1. The PRBS generator is not reset, so there is no initial

position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the

pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all

of the LVDS parallel outputs, so when the pattern is ‘1’ then all of the LVDS outputs are outputting ‘1’ and when

the pattern is 0 then all of the LVDS drivers output 0. To determine if the digital interface is operating properly

with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a shift-and-

compare until a matching sequence is confirmed.

7.3.8 Die Identification and Revision

A unique 64-bit die indentifier code can be read from registers 0x17 through 0x1E. An 8-bit die revision code is

available in register 0x1F.

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