ADS5400IPZP datasheet(40/58 Pages) TI2

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CLKP

CLKM

0.1 F

100W

Typical LVPECL

Clock Input

150W

ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

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Typical Application (continued)

Figure 38. Recommended Differential Clock Driving Circuit

8.2.1 Design Requirements

The ADS5400 requires a fully differential analog input with a full-scale range not to exceed 2 V peak to peak

differential, biased to a common mode voltage of 2.5 V. In addition the input circuit must provide proper

transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the

impedance of the ADC analog inputs should be considered as well.

The ADS5400 is capable of a typical SNR of 58.5 dBFS for input frequencies of about 125 MHz, which is well

under the Nyquist limit for this ADC operating at 1000 Msps. The amplifier and clocking solution will have a direct

impact on performance in terms of SNR, so the amplifier and clocking solution should be selected such that the

SNR performance of at least 58 dBFS is preserved.

8.2.2 Detailed Design Procedure

8.2.2.1 Clocking Source for ADS5400

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise, the thermal noise,

and the total jitter of the sample clock. Quantization noise is driven by the resolution of the ADC, which is 12 bits

for the ADS5400. Thermal noise is typically not noticeable in high speed pipelined converters such as the

ADS5400, but may be estimated by looking at the signal to noise ratio of the ADC with very low input frequencies

and using Equation 2 to solve for thermal noise. (For this estimation, we will take thermal noise to be zero. The

lowest frequency for which SNR is specified is 125 MHz. If we had an SNR specification for input frequencies

around 5 MHz then that SNR would be a good approximation for SNR due to thermal noise. This would be just

an approximation, and the lower the input frequency that has an SNR specification the better this approximation

would be.) The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher

input frequencies. For ADCs with higher resolution and typical SNR of 75 dBFS or so, thermal noise would be

more of a factor in overall performance. Quantization noise is also a limiting factor for SNR, as the theoretical

maximum achievable SNR as a function of the number of bits of resolution is set by Equation 1.

where

•

N = number of bits resolution.

(1)

For a 12-bit ADC, the maximum SNR = 1.76 + (6.02 × 12) = 74 dB. This is the number that we shall enter into

Equation 2 for quantization noise as we solve for total SNR for different amounts of clock jitter using Equation 2.

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