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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADS5400IPZP датащи(PDF) 10 Page - Texas Instruments |
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ADS5400IPZP датащи(HTML) 10 Page - Texas Instruments |
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10 / 58 page  ADS5400 SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016 www.ti.com Interleaving Adjustments (continued) Typical values at TA = 25°C, Minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DNL Differential linearity error -4 -2, +1 4 LSB INL Integral Non-Linearity error -8 -2, +4 8 LSB Min Gain Setting 1.52 VPP Max Gain Setting 2 VPP INPUT CLOCK FINE PHASE ADJUSTMENT Resolution 6 Bits LSB magnitude 116 fs DNL Differential linearity error -2 2.5 LSB INL Integral Non-Linearity error -2.5 4 LBS Max Fine Clock Skew setting 7.4 ps INPUT CLOCK COARSE PHASE ADJUSTMENT Resolution 5 Bits LSB magnitude 2.4 ps DNL Differential linearity error -1 1 LSB INL Integral Non-Linearity error -1 5 LSB Max Coarse Clock Skew 73 ps setting 6.7 Timing Requirements Typical values at TA = 25°C, Minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) (1). MIN NOM MAX UNIT ta Aperture delay 250 ps Uncertainty of sample point due to internal jitter Aperture jitter, rms 125 fs sources Bus A, using Single Bus Mode 7 Bus A, using Dual Bus Mode Aligned 7.5 Latency Cycles Bus B, using Dual Bus Mode Aligned 8.5 Bus A and B, using Dual Bus Mode Staggered 7.5 LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)(2) tCLK Clock period 1 10 ns tCLKH Clock pulse duration, high Assuming worst case 45/55 duty cycle 0.45 ns tCLKL Clock pulse duration, low Assuming worst case 55/45 duty cycle 0.45 ns tPD-CLKDIV2 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 2 mode 700 1200 1700 ps tPD-CLKDIV4 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 4 mode 700 1200 1700 ps Bus A data propagation tPD-ADATA CLKIN falling to Data Output transition 700 1400 2100 ps delay Bus B data propagation tPD-BDATA CLKIN falling to Data Output transition 700 1400 2100 ps delay (tCLK/2) - tSU-SBM (3) Setup time, single bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle 290p s 185p (1) Timing parameters are specified by design or characterization, but not production tested. (2) LVDS output timing measured with a differential 100- Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance is 3.5 pF. Measurement probes and other parasitics add ~1 pF. Total approximate capacitive load is 4.5 pF differential. All timing parameters are relative to the device pins, with the loading as stated. (3) In single bus mode at 1 GSPS (1-ns clock), the minimum output setup/hold times over process and temperature provide a minimum 700 ps of data valid window, with 300 ps of uncertainity. 10 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: ADS5400 |
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