ADS5400IPZP datasheet(28/58 Pages) TI2

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ADS5400

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

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7.3.9 Die Temperature Sensor

In register 0x05, the die temperature sensor can be enabled. The sensor is power controlled independently of

global powerdown, so that it and the SPI can be used to monitor the die temperature even when the remainder

of the ADC is in sleep mode. Register 0x08 is used to read values which can be mapped to the die temperature.

The exact mapping is detailed in the register map. Care should be taken not to exceed a maximum die

temperature of 150°C for prolonged periods of time to maintain the life of the device.

7.3.10 Interleaving

7.3.10.1 Gain Adjustment

A signal gain adjustment is available in registers 0x00 and 0x01. The allowable fullscale range for the ADC is

1.52 - 2VPP and can be set with 12-bit adjustment resolution across this range. For equal up/down gain

adjustment of the system and ADC gain mismatches, a nominal starting point of 1.75VPP could be programmed,

in which case ±250 mV of adjustment range would be provided.

7.3.10.2 Offset Adjustment

Analog offset adjustment is available in register 0x03 and 0x04. This provides ±30 mV of adjustment range with

9-bit adjustment resolution of 120uV per step. At production test, the default code for this register setting is set to

a value that provides 0 mV of ADC offset. For optimum spectral performance, it is not recommended to use more

than ±8mV adjustment from the default setting

7.3.10.3 Input Clock Coarse Phase Adjustment

Coarse adjustment is available in register 0x02. The typical range is approximately 73 ps with a resolution of

2.4ps.

7.3.10.4 Input Clock Fine Phase Adjustment

Fine adjustment is available in register 0x03. The typical range is approximately 7.4 ps with a resolution of 116fs.

7.4 Device Functional Modes

7.4.1 Output Bus and Clock Options

The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In

single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock

rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is

achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing

options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is

the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It

is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement

and offset binary are available output formats, in register 0x05.

The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid

timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board

capacitance on each LVDS pair.

7.4.2 Reset and Synchronization

Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data

output transition is undetermined because of the unknown startup logic level of the clock divider that generates

the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when

power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the

clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using

only one ADS5400 because a one sample uncertainty at startup is not usually a problem.

NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final

samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP.

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