ADS5400IPZP datasheet(41/58 Pages) TI2

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Amp Filter

FILTEROUT

SNR

10 log

20 log

Amp Filter

ADC

SNR

System

SNR

20 log

= -

(

) (

)

Jitter

Jitter,Ext .Clock_Input

Aperture _ ADC

[

]

(

)

Jitter

SNR

dBc

20 log 2

= -

p ´

Quantization _ Noise

Thermal _ Noise

Jitter

SNR

ADC

SNR

[dBc]

Log

= -

ADS5400

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SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Typical Application (continued)

(2)

The SNR limitation due to sample clock jitter can be calculated by Equation 3.

(3)

It is important to note that the clock jitter in Equation 3 is the total amount of clock jitter, whether the jitter source

is internal to the ADC itself or external due to the clocking source. The total clock jitter (TJitter) has two

components – the internal aperture jitter (125 fs for ADS5400) which is set by the noise of the clock input buffer,

and the external clock jitter from the clocking source and all associated buffering of the clock signal. Total clock

jitter can be calculated from the aperture jitter and the external clock jitter as in Equation 4.

(4)

External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass

filters at the clock input while a faster clock slew rate may at times also improve the ADC aperture jitter slightly.

The ADS5400 has an internal aperture jitter of 125 fs, which is largely fixed. The SNR depending on amount of

external jitter for different input frequencies is shown in Figure 39. Often the design requirements will list a target

SNR for a system, and Equation 2 through Equation 4 are then used to calculate the external clock jitter needed

from the clocking solution to meet the system objectives.

Figure 39 shows that with an external clock jitter of 200 fs rms, the expected SNR of the ADS5400 would be

greater than 58 dBFS at an input tone of 400 MHz, which is the assumed bandwidth for this design example.

Having less external clock jitter such as 150 fs rms or even 100 fs rms would result in an SNR that would exceed

our design target, but at possibly the expense of a more costly clocking solution. Having external clock jitter of

much greater than 200 fs rms or more would fail to meet our design target.

8.2.2.2 Amplifier Selection

The amplifier and any input filtering will have its own SNR performance, and the SNR performance of the

amplifier front end will combine with the SNR of the ADC itself to yield a system SNR that is less than that of the

ADC itself. System SNR can be calculated from the SNR of the amplifier conditioning circuit and the overall ADC

SNR as in Equation 5. In Equation 5, the SNR of the ADC would be the value derived from the datasheet

specifications and the clocking derivation presented in the previous section.

(5)

The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the noise specifications in the

datasheet for the amplifier, the amplitude of the signal and the bandwidth of the filter. The noise from the

amplifier is band-limited by the filter and the rolloff of the filter will depend on the order of the filter, so it is

convenient to replace the filter rolloff with an equivalent brick-wall filter bandwidth. For example, a 1st order filter

may be approximated by a brick-wall filter with bandwidth of 1.57 times the bandwidth of the 1st order filter. We

will assume a 1st order filter for this design. The amplifier and filter noise can be calculated using Equation 6.

where

•

VO= the amplifier output signal (which will be full scale input of the ADC expressed in rms)

•

EFILTEROUT = ENAMPOUT × √ENB

–

ENAMPOUT = the output noise density of the LMH3401 (3.4 nV/√Hz)

–

ENB = the brick-wall equivalent noise bandwidth of the filter

(6)

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