ADS5400IPZP datasheet(5/58 Pages) TI2

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ADS5400

www.ti.com

SLAS611C – OCTOBER 2009 – REVISED JANUARY 2016

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

3, 6, 8,

84, 88,

91, 93,

AGND

Ground

Analog ground

96, 98,

100

Analog differential input signal (positive, negative). Includes 100-

Ω differential load on-

94, 95

AINP, AINN

Input

chip.

2, 7, 9,

AVDD3

Supply

Analog power supply (3.3 V)

1, 76, 86,

90, 92,

AVDD5

Supply

Analog power supply (5 V)

97, 99

4, 5

CLKINP, CLKINN

Input

Differential input clock (positive, negative). Includes 160-

Ω differential load on-chip.

CLKOUTAN,

60, 61

Output

Bus A, Clock output (Data ready), LVDS output pair

CLKOUTAP

CLKOUTBN,

26, 27

Output

Bus B, Clock output (Data ready), LVDS output pair

CLKOUTBP

Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N =

46, 47

DA0N, DA0P

Output

negative output)

48-49,

52-59,

DA1N–DA10N,

Output

Bus A, LVDS digital output pairs (bits 1- 10)

62-63,

DA1P-DA10P

66-73

74, 75

DA11N, DA11P

Output

Bus A, LVDS digital output pair, most-significant bit (MSB)

Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N =

40, 41

DB0N, DB0P

Output

negative output)

14-23,

DB1N–DB10N,

Output

Bus B, LVDS digital output pairs (bits 1- 10)

28-37

DB1P-DB10P

12, 13

DB11N, DB11P

Output

Bus B, LVDS digital output pair, most-significant bit (MSB)

25, 39,

DGND

Ground

Digital ground

51, 65

24, 38,

DVDD3

Supply

Output driver power supply (3.3 V)

50, 64

Enable single output bus mode (2-bus mode is default), active high. This pin is logic

81(1)

ENA1BUS

Input

OR'd with addr 0x02h bit<0>.

Enable External Reference Mode, active high. Device uses an external voltage reference

83(1)

ENEXTREF

Input

when high. This pin is logic OR'd with addr 0x05h bit<2>.

Enable Powerdown, active high. Places the converter into power-saving sleep mode

82(1)

ENPWD

Input

when high. This pin is logic OR'd with addr 0x05h bit<6>.

Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess

44, 45

OVRAN, OVRAP

Output

of the full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register

0x05.

Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess

42, 43

OVRBN, OVRBP

Output

of the full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register

0x05.

Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state,

this is used for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled

RESETN,

10, 11

Input

in register 0x05, this input also provides a SYNC time-stamp with the data sample

RESETP

present when RESET is clocked by the ADC, as well as CLKOUT polarity reset. Includes

100-

Ω differential load on-chip.

SCLK

Input

Serial interface clock.

Active low serial data enable, always an input. Use to enable the serial interface. Internal

SDENB

Input

100k

Ω pull-up resistor.

Bidirectional serial interface data in 3-pin mode (default) for programming/reading

SDIO

Input/Output

internal registers. In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.

(1)

This pin contains an internal ~40k

Ω pull-down resistor, to ground.

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