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ADC32RF44IRMPR датащи(PDF) 92 Page - Texas Instruments |
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ADC32RF44IRMPR датащи(HTML) 92 Page - Texas Instruments |
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92 / 135 page ![]() 92 ADC32RF44 SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017 www.ti.com Product Folder Links: ADC32RF44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table 69. Register 032h-035h Field Descriptions Bit Field Type Reset Description 7-2 SEL EMP LANE R/W 0h These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in dB is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 0 = 0 dB 1 = –1 dB 3 = –2 dB 7 = –4.1 dB 15 = –6.2 dB 31 = –8.2 dB 63 = –11.5 dB 1-0 0 W 0h Must write 0 9.5.11.10 Register 036h (address = 036h), JESD Digital Page Figure 162. Register 036h 7 6 5 4 3 2 1 0 80X MODE EN CMOS SYNCB 0 0 0 0 0 0 R/W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 70. Register 036h Field Descriptions Bit Field Type Reset Description 7 80X MODE EN R/W 0h This bit enables the 80X mode. 0 = 80X mode disable 1 = 80X mode enable 6 CMOS SYNCB R/W 0h This bit enables single-ended control of SYNCB using the GPIO4 pin (pin 63). The differential SYNCB input is ignored. 0 = Differential SYNCB input 1 = Single-ended SYNCB input using pin 63 5-0 0 W 0h Must write 0 9.5.11.11 Register 037h (address = 037h), JESD Digital Page Figure 163. Register 037h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PLL MODE W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 71. Register 037h Field Descriptions Bit Field Type Reset Description 7-2 0 W 0h Must write 0 1-0 PLL MODE R/W 0h These bits select the PLL multiplication factor; see the JESD tables in the JESD204B Frame Assembly section for settings. 00 = 20X mode 01 = 16X mode 10 = 40X mode (write register 16h with 70h) 11 = 80X mode (the 40X_80X MODE bit in register 16h must also be set) |
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