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ADC32RF44IRMPR датащи(PDF) 28 Page - Texas Instruments

номер детали ADC32RF44IRMPR
подробное описание детали  ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
PDF  135 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

ADC32RF44IRMPR датащи(HTML) 28 Page - Texas Instruments

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Input Clock
Divider
(Divide-by-4)
ASSERT SYSREF REG
(In Master Page)
SEL SYSREF REG
(In Master Page)
0
1
CLKIN
(CLKP-CLKM)
SYSREF
(SYSREFP-SYSREFM)
DLL
NCO,
JESD Interface
(LMFC Counter)
MASK CLKDIV SYSREF
(In JESD Digital Page)
MASK NCO SYSREF
(In JESD Digital Page)
PDN SYSREF
(In Master Page)
28
ADC32RF44
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
www.ti.com
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Feature Description (continued)
9.3.3.1 Using SYSREF
The ADC32RF44 uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of
the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or
through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change
in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 68.
Figure 68. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter
The ADC32RF44 samples the SYSREF signal on the input clock rising edge. Required setup and hold time are
listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,
whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after
disregarding the first two assertions, as shown in Table 1.
Table 1. Asserting SYSREF
SYSREF ASSERTION INDEX
ACTION
INPUT CLOCK DIVIDER
NCO PHASE
LMFC COUNTER
1
Gets reset
Does not get reset
Does not get reset
2
Gets reset
Does not get reset
Does not get reset
3
Gets reset
Gets reset
Gets reset
4 and onwards
Gets reset
Gets reset
Gets reset



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