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ADC32RF44IRMPR датащи(PDF) 90 Page - Texas Instruments

номер детали ADC32RF44IRMPR
подробное описание детали  ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
PDF  135 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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ADC32RF44IRMPR датащи(HTML) 90 Page - Texas Instruments

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Digital JESD Logic
D0
D1
D2
D3
Output Mux
Lane0
Lane1
Lane2
Lane3
20x
(PLL Mode)
90
ADC32RF44
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
www.ti.com
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
9.5.11.7 Register 016h (address = 016h), JESD Digital Page
Figure 155. Register 016h
7
6
5
4
3
2
1
0
LANE 0
LANE 1
LANE 2
LANE 03
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 66. Register 016h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
LANE 0
R/W
0h
For 80X mode: set these bits as 70h. Also set the 80X MODE
EN register bit.
For 40X mode: set these bits as 70h.
For 20X mode: these bits can be used to swap the data on
output lanes as shown in Table 67 and Figure 156.
5-4
LANE 1
R/W
0h
3-2
LANE 2
R/W
0h
1-0
LANE 3
R/W
0h
Table 67. Swapping Data on Output Lanes for 20X Serialization
REGISTER BIT
LANE 0
OUTPUT
LANE0
CARRIES
REGISTER BIT
LANE 1
OUTPUT
LANE1
CARRIES
REGISTER BIT
LANE 2
OUTPUT
LANE2
CARRIES
REGISTER BIT
LANE 3
OUTPUT
LANE3
CARRIES
00
D0
00
D1
00
D2
00
D3
01
D1
01
D2
01
D3
01
D0
10
D2
10
D3
10
D0
10
D1
11
D3
11
D0
11
D1
11
D2
Figure 156. Output Lane Multiplexer



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