ADC32RF44IRMPR datasheet(6/135 Pages) TI2

6 / 135 page

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

www.ti.com

Product Folder Links: ADC32RF44

Submit Documentation Feedback

(1)

See the Power Consumption in Different Modes section for more details.

(2)

Full-scale signal is applied to the analog inputs of all active channels.

(3)

When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best

performance.

(4)

Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.

(5)

See Figure 57.

7.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =

1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER CONSUMPTION(1) (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode(2))

IAVDD19

1.9-V analog supply current

12-bit, bypass mode, fS = 2.6 GSPS

1730

1969

IAVDD

1.15-V analog supply current

12-bit, bypass mode, fS = 2.6 GSPS

860

1079

IDVDD

1.15-V digital supply current

12-bit, bypass mode, fS = 2.6 GSPS

1416

1846

Power dissipation

12-bit, bypass mode, fS = 2.6 GSPS

5.9

6.95

Global power-down power

dissipation

360

ANALOG INPUTS

Resolution

Bits

Differential input full-scale

1.35

VPP

VIC

Input common-mode voltage

1.2(3)

RIN

Input resistance

Differential resistance at dc

CIN

Input capacitance

Differential capacitance at dc

VCM common-mode voltage output

1.2

Analog input bandwidth

(–3-dB point)

ADC driven with 50-Ω source

3200

MHz

ISOLATION

Crosstalk isolation between channel

A and channel B(4)

fIN = 100 MHz

100

dBc

fIN = 900 MHz

fIN = 1800 MHz

fIN = 2700 MHz

fIN = 3500 MHz

CLOCK INPUT(5)

Input clock frequency

1.5

2.6

GHz

Differential (peak-to-peak) input

clock amplitude

0.5

1.5

2.5

VPP

Input clock duty cycle

45%

50%

55%

Internal clock biasing

1.0

Internal clock termination

(differential)

100

ADC32RF44IRMPR датащи(PDF) 6 Page - Texas Instruments

ADC32RF44IRMPR датащи(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL