ADC32RF44IRMPR datasheet(22/135 Pages) TI2

22 / 135 page

ADC

INAP,

INAM

SYSREFP,

SYSREFM

CLKINP,

CLKINM

PLL

Buffer

INBP,

INBM

Buffer

DB[1:0]P,

DB[1:0]M

DA[1:0]P,

DA[1:0]M

DA[3:2]P,

DA[3:2]M

DB[3:2]P,

DB[3:2]M

GPIO[4:1]

ADC

NCO

CTRL

SYNCBP,

SYNCBM

NCO

FOVR

NCO

ADC

Digital Block

Interleave

Correction

Power

Detection

Digital Block

Interleave

Correction

Power

Detection

Clock

Divider

SPI

and

Control

RESET

SCLK

SDATA

SEN

PDN

SDO

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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Product Folder Links: ADC32RF44

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9 Detailed Description

9.1 Overview

The ADC32RF44 is a dual, 14-bit, 2.6-GSPS, analog-to-digital converter (ADC) followed by a multi-band digital

down-converter (DDC) that can be bypassed, and a back-end JESD204B digital interface.

The ADCs are preceded by an input buffer and on-chip termination to provide a uniform input impedance over a

large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection

against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with

background, analog and digital, and interleaving correction.

The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of

interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,

16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be

controlled through the SPI or GPIO pins. The ADC32RF44 also provides three different power detectors on-chip

with alarm outputs in order to support external automatic gain control (AGC) loops.

The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized,

and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN,

SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B

interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link.

All features of the ADC32RF44 are configurable through the SPI.

9.2 Functional Block Diagram

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