ADC32RF44IRMPR datasheet(64/135 Pages) TI2

64 / 135 page

R/W, M, P, CH, Bits Decoder

Initiate an SPI Cycle

(1)

Master Page

(PDN,

DC Coupling,

SYSREF Delay,

JESD Swing,

initialization

Registers)

Keep M, P, R/W =

0 when writing to

this page, and

keep these bits =

1 when reading

from this page

Value 690000h

Main

Digital Page for

ChA

(Nyquist Zone)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading

from this page

JESD

Digital Page

(JESD

Configuration)

Keep M, P = 1,

CH = 0 for ChB,

CH = 1 for ChA

Keep R/W = 0

when writing to

this page, and = 1

when reading

from this page

M = 1

M = 0

Value 04h

Value FFh

Analog Bank

(3)

Digital Bank

Select DIGITAL Bank Page

(Address 04h, Address 03h, and Address 02h bits DIGITAL BANK PAGE SEL[23:0],

Keep M = 1, P = 0)

Select ADC Page

(Address 11h, Value FFh,

Keep M, P = 0)

General Register

(Address 00h,

Keep M, P = 0)

(Global Reset)

General Register

(Address 05h,

Keep M = 1, P = 0)

st SPI Cycle:

Page Selection

nd SPI Cycle:

Page Programing

Select Master Page

(Address 12h, value 04h,

Keep M, P = 0)

ADC Page

(Slow Speed

Enable,

Initialization

Registers)

Keep M, P, R/W =

0 when writing to

this page, and

keep these bits =

1 when reading

from this page

Main

Digital Page for

ChB

(Nyquist Zone)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading from

this page

Offset Corr Page

ChA

(Offset Corr)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading from

this page

SPI cycle:

These Pages

are directly

programmed

in one SPI

cycle.

R/W

SDIN

SCLK

SEN

A11

A10

SPI Cycle

Direct

Addressing

Pages:

DDC and

Power

Detector

(2)

Value 610000h

Value 610100h

Value 610005h

Value 610105h

Value 680000h

Value 680100h

Offset Corr Page

ChB

(Offset Corr)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading from

this page

Digital Gain Page

ChA

(Digital Gain)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading from

this page

Digital Gain Page

ChB

(Digital Gain)

Keep

M, P, CH bits =

(1, 1, 0).

R/W = 0 when

writing to this

page, and = 1

when reading from

this page

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

www.ti.com

Product Folder Links: ADC32RF44

Submit Documentation Feedback

9.5 Register Maps

The ADC32RF44 contains two main SPI banks. The analog SPI bank provides access to the ADC core and the digital SPI bank controls the digital blocks

(including the serial JESD interface). Figure 121 and Figure 122 provide a conceptual view of the SPI registers inside the ADC32RF44. The analog SPI

bank contains the master and ADC pages. The digital SPI bank is divided into multiple pages (the main digital, digital gain, decimation filter, JESD digital,

and power detector pages).

In general, SPI writes are completed in two steps. The first step is to access the necessary page. The second step is to program the desired register in that page. When

a page is accessed, the registers in that page can be programmed multiple times.

Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle.

The CH bit is a don't care bit and is recommended to be kept at 0.

Figure 121. SPI Registers, Two-Step Addressing

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