ADC32RF44IRMPR datasheet(45/135 Pages) TI2

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THHH

THHL

BLKPKDET

Crossing Detector Time Period

Crossing Detector Counter

Crossing Detector Counter Threshold

IIR PK DET

Combine

BLKPKDETH

BLKPKDETL

BLKPKDETHL

2-Bit Mode

FILT0LP

SEL

Time

Constant

>FIL0THH

>FIL0THL

1 or 2-Bit

Mode

Time

Constant

>FIL1THH

>FIL1THL

1 or 2-Bit

Mode

IIR PK DET0

IIR PK DET1

2-Bit Mode

10: High

00: Mid

01: Low

1-Bit Mode

With Hysteresis and Dwell

1: High

0: Low

Peak Over

8 Samples

ADC

Output

Block:

Peak Over N

Samples (S`)

fS/8

fS/(8N)

BLKPKDET

N = [1..2

16]

>THHigh

>THLow

Hysteresis

and DWELL

>TLHigh

>TLLow

Hysteresis

and DWELL

BLKTHHH,

BLKTHHL,

BLKTHLH,

BLKTHLL

DWELL

IIR LPF

ADC32RF44

www.ti.com

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

Product Folder Links: ADC32RF44

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9.3.8.2 Crossing Detector

In this detector mode the peak is computed over eight samples of the ADC output. Next, the peak for a block of

N samples (N × S`) is computed over a programmable block length and then the peak is compared against two

sets of programmable thresholds (with hysteresis). The crossing detector counts how many fS / 8 clock cycles

that the block detector outputs are set high over a programmable time period and compares the counter value

against the programmable thresholds. The alarm outputs are updated at the end of the time period, routed to the

GPIO pins, and held in that state through the next cycle, as shown in Figure 105 and Figure 106. Alternatively, a

2-bit format can be used but (because the ADC32RF44 has four GPIO pins available) this feature uses all four

pins for a single channel.

Figure 105. Crossing Detector Implementation

Figure 106. Crossing Detector Timing Diagram

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