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ADC32RF44IRMPR датащи(PDF) 29 Page - Texas Instruments

номер детали ADC32RF44IRMPR
подробное описание детали  ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
PDF  135 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
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ADC32RF44IRMPR датащи(HTML) 29 Page - Texas Instruments

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CLKIN
SYSREF
1
st SYSREF pulse.
Only the input clock
divider is reset.
tDLL
(Must be Kept > 40 Ps)
2
nd SYSREF pulse. If
the MASK CLKDIV bit is
set, the clock divider
ignores this pulse and
any subsequent
SYSREF pulses.
3
rd SYSREF pulse.
The NCO phase and
LMFC counter are reset.
MASK CLKDIV SYSREF Register Bit
0
1 (The input clock divider ignores the SYSREF pulses.)
MASK NCO SYSREF Register Bit
(1)
0
1 (The NCO and LMFC counter of the JESD interface
ignore the SYSREF pulses.)
4
th SYSREF pulse (and
subsequent pulses).
Ignored by the input clock
divider, NCO, and the JESD
interface.
29
ADC32RF44
www.ti.com
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
The SESREF use-cases can be classified broadly into two categories:
1. SYSREF is applied as aperiodic multi-shot pulses.
Figure 69 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.
Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.
Figure 69. SYSREF Used as a Periodic, Finite Number of Pulses
After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the tDLL time (>
40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider
by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase
and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going
to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted
resets.



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