ADC32RF44IRMPR datasheet(44/135 Pages) TI2

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THHH

THHL

BLKPKDET

DWELL Time

ADC32RF44

SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017

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Figure 104. Peak Power Detector Timing Diagram

Table 8 shows the register configurations required to set up the absolute peak power detector. The detector

operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples.

The automatic gain control (AGC) modes can be configured separately for channel A (54xxh) and channel B

(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).

Table 8. Registers Required for the Peak Power Detector

ADDRESS

DESCRIPTION

PKDET EN

5400, 5C00h

Enables peak detector

BLKPKDET

5401h, 5402h,

5403h, 5C01h,

5C02h, 5C03h

Sets the block length N of number of samples (S`). Number of actual ADC samples is 8X this

value: N is 17 bits: 1 to 216.

BLKTHHH,

BLKTHHL,

BLKTHLH,

BLKTHLL

5407h, 5408h,

5409h, 540Ah,

5C07h, 5C08h,

5C09h, 5C0Ah

Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is

equivalent to the peak amplitude).

For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then set 5407h and

5C07h = CBh.

DWELL

540Bh, 540Ch,

5C0Bh, 5C0Ch

When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak

detector output flags are set. In order to be reset, the computed block peak must remain

continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by

the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles.

OUTSEL

GPIO[4:1]

5432h, 5433h,

5434h, 5435h

Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register.

IODIR

5437h

Selects the direction for the four GPIO pins; common register.

RESET AGC

542Bh, 5C2Bh

After configuration, reset the AGC module to start operation.

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