UPSD3422 datasheet(48/293 Pages) STMICROELECTRONICS

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Dual data pointers

uPSD34xx

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11.2

Data pointer mode register, DPTM (86h)

The two “background” data pointers, DPTR0 and DPTR1, can be configured to

automatically increment, decrement, or stay the same after a MOVX instruction accesses

the DPTR Register. Only the currently selected pointer will be affected by the increment or

decrement. This feature is controlled by the DPTM Register defined in Table 14.

The automatic increment or decrement function is effective only for the MOVX instruction,

and not MOVC or any other instruction that uses the DTPR Register.

11.2.1

Firmware example

The 8051 assembly code illustrated in Table 15 shows how to transfer a block of data bytes

from one XDATA address region to another XDATA address region. Auto-address

incrementing and auto-pointer toggling will be used.

Table 14.

DPTM: data pointer mode register (SFR 86h, reset value 00h)

Table 15.

8051 assembly code example

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

MD11

MD10

MD01

MD00

Bit

Symbol

R/W

Definition

7-4

–

Reserved

3-2

MD[11:10]

R,W

DPTR1 Mode Bits

00: DPTR1 No Change

01: Reserved

10: Auto Increment

11: Auto Decrement

1-0

MD[01:00]

R,W

DPTR0 Mode Bits

00: DPTR0 No Change

01: Reserved

10: Auto Increment

11: Auto Decrement

MOV

R7, #COUNT

; initialize size of data block to transfer

MOV

DPTR,

#SOURCE_ADDR

; load XDATA source address base into DPTR0

MOV

85h, #01h

; load DPTC to access DPTR1 pointer

MOV

DPTR, #DEST_ADDR ; load XDATA destination address base into DPTR1

MOV

85h, #40h

; load DPTC to access DPTR0 pointer and auto

toggle

MOV

86h, #0Ah

; load DPTM to auto-increment both pointers

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