UPSD3422 datasheet(87/293 Pages) STMICROELECTRONICS

87 / 293 page

uPSD34xx

Standard 8032 timer/counters

87/293

Standard 8032 timer/counters

There are three 8032-style 16-bit Timer/Counter registers (Timer 0, Timer 1, Timer 2) that

can be configured to operate as timers or event counters.

There are two additional 16-bit Timer/Counters in the Programmable Counter Array (PCA),

see Section 27.1: PCA block on page 175 for details.

20.1

Standard timer SFRs

Timer 0 and Timer 1 have very similar functions, and they share two SFRs for control:

●

TCON (Table 41 on page 88)

●

TMOD (Table 42 on page 90).

Timer 0 has two SFRs that form the 16-bit counter, or that can hold reload values, or that

can scale the clock depending on the timer/counter mode:

●

TH0 is the high byte, address 8Ch

●

TL0 is the low byte, address 8Ah

Timer 1 has two similar SFRs:

●

TH1 is the high byte, address 8Dh

●

TL1 is the low byte, address 8Bh

Timer 2 has one control SFR:

●

T2CON (Table 43 on page 93)

Timer 2 has two SFRs that form the 16-bit counter, and perform other functions:

●

TH2 is the high byte, address CDh

●

TL2 is the low byte, address CCh

Timer 2 has two SFRs for capture and reload:

●

RCAP2H is the high byte, address CBh

●

RCAP2L is the low byte, address CAh

20.2

Clock sources

When enabled in the “Timer” function, the Registers THx and TLx are incremented every

1/12 of the oscillator frequency (fOSC). This timer clock source is not effected by MCU clock

dividers in the CCON0, stalls from PFQ/BC, or bus transfer cycles. Timers are always

clocked at 1/12 of fOSC.

When enabled in the “Counter” function, the Registers THx and TLx are incremented in

response to a 1-to-0 transition sampled at their corresponding external input pin: pin C0 for

Timer 0; pin C1 for Timer 1; or pin T2 for Timer 2. In this function, the external clock input pin

is sampled by the counter at a rate of 1/12 of fOSC. When a logic '1' is determined in one

sample, and a logic '0' in the next sample period, the count is incremented at the very next

sample period (period1: sample=1, period2: sample=0, period3: increment count while

continuing to sample). This means the maximum count rate is 1/24 of the fOSC. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level is

sampled at least once before it changes, it should be active for at least one full sample

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