UPSD3422 datasheet(55/293 Pages) STMICROELECTRONICS

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uPSD34xx

Interrupt system

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13.1

Individual interrupt sources

13.1.1

External interrupts Int0 and Int1

External interrupt inputs on pins EXTINT0 and EXTINT1 (pins 3.2 and 3.3) are either edge-

triggered or level-triggered, depending on bits IT0 and IT1 in the SFR named TCON.

When an external interrupt is generated from an edge-triggered (falling-edge) source, the

appropriate flag bit (IE0 or IE1) is automatically cleared by hardware upon entering the ISR.

When an external interrupt is generated from a level-triggered (low-level) source, the

appropriate flag bit (IE0 or IE1) is NOT automatically cleared by hardware.

13.1.2

Timer 0 and 1 overflow interrupt

Timer 0 and Timer 1 interrupts are generated by the flag bits TF0 and TF1 when there is an

overflow condition in the respective Timer/Counter register (except for Timer 0 in Mode 3).

13.1.3

Timer 2 overflow interrupt

This interrupt is generated to the MCU by a logical OR of flag bits, TF2 and EXE2. The ISR

must read the flag bits to determine the cause of the interrupt.

●

TF2 is set by an overflow of Timer 2.

●

EXE2 is generated by the falling edge of a signal on the external pin, T2X (pin P1.1).

13.1.4

UART0 and UART1 interrupt

Each of the UARTs have identical interrupt structure. For each UART, a single interrupt is

generated to the MCU by the logical OR of the flag bits, RI (byte received) and TI (byte

transmitted).

The ISR must read flag bits in the SFR named SCON0 for UART0, or SCON1 for UART1 to

determine the cause of the interrupt.

13.1.5

SPI interrupt

The SPI interrupt has four interrupt sources, which are logically ORed together when

interrupting the MCU. The ISR must read the flag bits to determine the cause of the

interrupt.

A flag bit is set for: end of data transmit (TEISF); data receive overrun (RORISF); transmit

buffer empty (TISF); or receive buffer full (RISF).

13.1.6

I2C interrupt

The flag bit INTR is set by a variety of conditions occurring on the I2C interface: received

own slave address (ADDR flag); received general call address (GC flag); received STOP

condition (STOP flag); or successful transmission or reception of a data byte.The ISR must

read the flag bits to determine the cause of the interrupt.

13.1.7

ADC interrupt

The flag bit AINTF is set when an A-to-D conversion has completed.

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