UPSD3422 datasheet(85/293 Pages) STMICROELECTRONICS

85 / 293 page

uPSD34xx

Supervisory functions

85/293

To prevent the WDT from timing out and generating a reset, firmware must repeatedly write

some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the

upper 8 bits of the 24-bit counter are loaded with the written value, and the lower 16 bits of

the counter are cleared to 0000h.

The WDT time-out period can be adjusted by writing a value other that 00h to WDRST. For

example, if WDRST is written with 04h, then the WDT will start counting 040000h, 040001h,

040002h, and so on for each MCU machine cycle. In this example, the WDT time-out period

is shorter than if WDRST was written with 00h, because the WDT is an up-counter. A value

for WDRST should never be written that results in a WDT time-out period shorter than the

time required to complete the longest code task in the application, else unwanted WDT

overflows will occur.

Figure 24.

Watchdog counter

The formula to determine WDT time-out period is:

WDTPERIOD = tMACH_CYC x NOVERFLOW

NOVERFLOW is the number of WDT up-counts required to reach FFFFFFh. This is

determined by the value written to the SFR, WDRST.

tMACH_CYC is the average duration of one MCU machine cycle. By default, an MCU machine

cycle is always 4 MCU_CLK periods for uPSD34xx, but the following factors can sometimes

add more MCU_CLK periods per machine cycle:

●

The number of MCU_CLK periods assigned to MCU memory bus cycles as determined

in the SFR, BUSCON. If this setting is greater than 4, then machine cycles have

additional MCU_CLK periods during memory transfers.

●

Whether or not the PFQ/BC circuitry issues a stall during a particular MCU machine

cycle. A stall adds more MCU_CLK periods to a machine cycle until the stall is

removed.

tMACH_CYC is also affected by the absolute time of a single MCU_CLK period. This number

is fixed by the following factors:

●

Frequency of the external crystal, resonator, or oscillator: (fOSC)

●

Bit settings in the SFR CCON0, which can divide fOSC and change MCU_CLK

As an example, assume the following:

fOSC is 40MHz, thus its period is 25ns.

CCON0 is 10h, meaning no clock division, so the period of MCU_CLK is also 25ns.

BUSCON is C1h, meaning the PFQ and BC are enabled, and each MCU memory bus

cycle is 4 MCU_CLK periods, adding no additional MCU_CLK periods to MCU machine

cycles during memory transfers.

Assume there are no stalls from the PFQ/BC. In reality, there are occational stalls but

their occurance has minimal impact on WDT timeout period.

WDRST contains 00h, meaning a full 224 up-counts are required to reach FFFFFh and

generate a reset.

8-bits

SFR, WDRST

AI09604

UPSD3422 датащи(PDF) 85 Page - STMicroelectronics

UPSD3422 датащи(HTML) 85 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL