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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPSD3422 датащи(PDF) 62 Page - STMicroelectronics |
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UPSD3422 датащи(HTML) 62 Page - STMicroelectronics |
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62 / 293 page  MCU clock generation uPSD34xx 62/293 Table 22. CCON0: Clock Control Register (SFR F9h, reset value 50h) Table 23. CCON1 PLL Control Register (SFR FAh, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLM[4] PLLEN UPLLCE DBGCE CPUAR CPUPS[2:0] Bit Symbol R/W Definition 7 PLLM[4] R,W Upper bit of the 5-bit PLLM[4:0] Multiplier (Default: '0' for PLLM = 00h) 6 PLLEN R,W PLL Enable 0 = Disable PLL operation 1 = Enable PLL operation (Default condition after reset) 5 UPLLCE R,W USB Clock Enable 0 = USB clock is disabled (Default condition after reset) 1 = USB clock is enabled 4DBGCE R,W Debug Unit Breakpoint Comparator Enable 0 = JTAG Debug Unit comparators are disabled 1 = JTAG Debug Unit comparators are enabled (Default condition after reset) 3 CPUAR R,W Automatic MCU Clock Recovery 0 = There is no change of CPUPS[2:0] when an interrupt occurs. 1 = Contents of CPUPS[2:0] automatically become 000b whenever any interrupt occurs. 2:0 CPUPS R,W MCUCLK Pre-Scaler 000b: fMCU = fOSC (Default after reset) 001b: fMCU = fOSC/2 010b: fMCU = fOSC/4 011b: fMCU = fOSC/8 100b: fMCU = fOSC/16 101b: fMCU = fOSC/32 110b: fMCU = fOSC/1024 111b: fMCU = fOSC/2048 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLM[3:0] PLLD[3:0] Bit Symbol R/W Definition 7:4 PLLM[3:0] R,W Lower 4 bits of the 5-bit PLLM[4:0] Multiplier (Default after reset: PLLM = 00h) PLLM[4] is in the CCON0 Register. 3:0 PLLD[3:0] R,W 4-bit PLL Divider (Default after reset: PLLD = 0h) |
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