UPSD3422 datasheet(63/293 Pages) STMICROELECTRONICS

63 / 293 page

uPSD34xx

Power saving modes

63/293

Power saving modes

The uPSD34xx is a combination of two die, or modules, each module having its own current

consumption characteristics. This section describes reduced power modes for the MCU

Module. See Section 28.1.16: Power management on page 191 for reduced power modes

of the PSD Module. Total current consumption for the combined modules is determined in

the DC specifications at the end of this document.

The MCU Module has three software-selectable modes of reduced power operation.

●

Idle Mode

●

Power-down Mode

●

Reduced Frequency Mode

15.1

Idle Mode

Idle Mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle Mode

blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to

disable all unused peripherals, before entering Idle mode (such as the ADC and the Debug

Unit breakpoint comparators). The following functions remain fully active during Idle Mode

(except if disabled by SFR settings).

●

External Interrupts INT0 and INT1

●

Timer 0, Timer 1 and Timer 2

●

Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, but not the WTD

●

ADC

●

I2C Interface

●

UART0 and UART1 Interfaces

●

SPI Interface

●

Programmable Counter Array

●

USB Interface

An interrupt generated by any of these peripherals, or a reset generated from the

supervisor, will cause Idle Mode to exit and the 8032 MCU will resume normal operation.

The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle Mode.

To enter Idle Mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR

named PCON, shown in Table 26 on page 66. This is the last instruction executed in normal

operating mode before Idle Mode is activated. Once in Idle Mode, the MCU status is entirely

preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA.

The following are factors related to Idle Mode exit:

●

Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware,

terminating Idle Mode. The interrupt is serviced, and following the Return from Interrupt

instruction (RETI), the next instruction to be executed will be the one which follows the

instruction that set the IDL bit in the PCON SFR.

●

After a reset from the supervisor, the IDL bit is cleared, Idle Mode is terminated, and

the MCU restarts after three MCU machine cycles.

UPSD3422 датащи(PDF) 63 Page - STMicroelectronics

UPSD3422 датащи(HTML) 63 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL