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UPSD3422 датащи(PDF) 83 Page - STMicroelectronics |
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UPSD3422 датащи(HTML) 83 Page - STMicroelectronics |
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83 / 293 page ![]() uPSD34xx Supervisory functions 83/293 19 Supervisory functions Supervisory circuitry on the MCU Module will issue an internal reset signal to the MCU Module and simultaneously to the PSD Module as a result of any of the following four events: ● The external RESET_IN pin is asserted ● The Low Voltage Detect (LVD) circuitry has detected a voltage on VCC below a specific threshold (power-on or voltage sags) ● The JTAG Debug interface has issued a reset command ● The Watch Dog Timer (WDT) has timed out The resulting internal reset signal, MCU_RESET, will force the 8032 into a known reset state while asserted, and then 8032 program execution will jump to the reset vector at program address 0000h just after MCU_RESET is deasserted. The MCU Module will also assert an active low internal reset signal, RESET, to the PSD Module. If needed, the signal RESET can be driven out to external system components through any PLD output pin on the PSD Module. When driving this “RESET_OUT” signal from a PLD output, the user can choose to make it either active-high or active-low logic, depending on the PLD equation. 19.1 External reset input pin, RESET_IN The RESET_IN pin can be connected directly to a mechanical reset switch or other device which pulls the signal to ground to invoke a reset. RESET_IN is pulled up internally and enters a Schmitt trigger input buffer with a voltage hysteresis of VRST_HYS for immunity to the effects of slow signal rise and fall times, as shown in Figure 23. RESET_IN is also filtered to reject a voltage spike less than a duration of tRST_FIL. The RESET_IN signal must be maintained at a logic '0' for at least a duration of tRST_LO_IN while the oscillator is running. The resulting MCU_RESET signal will last only as long as the RESET_IN signal is active (it is not stretched). Refer to the Supervisor AC specifications in Table 178 on page 279 at the end of this document for these parameter values. Figure 23. Supervisor reset generation Q S MCU Clock Sync Noise Filter VCC PIN PULL-UP DELAY, tRST_ACTV R AI09603 RESET_IN RESET to PSD Module MCU_RESET to MCU and Peripherals LVD JTAG Debug WDT |
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