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UPSD3422 датащи(PDF) 56 Page - STMicroelectronics |
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UPSD3422 датащи(HTML) 56 Page - STMicroelectronics |
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56 / 293 page ![]() Interrupt system uPSD34xx 56/293 13.1.8 PCA interrupt The PCA has eight interrupt sources, which are logically ORed together when interrupting the MCU.The ISR must read the flag bits to determine the cause of the interrupt. ● Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0 respectively. ● Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1 and INTF0 respectively. Tables 17 through Table 20 on page 58 have detailed bit definitions of the interrupt system SFRs. 13.1.9 USB Interrupt The USB interrupt has multiple sources. The ISR must read the USB Interrupt Flag Registers (UIF0-3) to determine the source of the interrupt. The USB interrupt can be activated by any of the following four group of interrupt sources: ● Global: the interrupt flag is set when any of the following events occurs: USB Reset, USB Suspend, USB Resume, and End of Packet; ● In FIFO: the interrupt flag is set when any of the End Point In FIFO becomes empty; ● Out FIFO: the interrupt flag is set when any of the End Point Out FIFO becomes full; and ● In FIFO NAK: the interrupt flag is set when any of the End Point In FIFO is not ready for an IN (in-bound) packet. Table 17. IE: interrupt enable register (SFR A8h, reset value 00h) Note: 1 1 = Enable Interrupt, 0 = Disable Interrupt Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EA – ET2 ES0 ET1 EX1 ET0 EX0 Bit Symbol R/W Function 7EA R,W Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt source can be individually enabled or disabled by setting or clearing its enable bit. 6– R,W Do not modify this bit. It is used by the JTAG debugger for instruction tracing. Always read the bit and write back the same bit value when writing this SFR. 5(1) ET2 R,W Enable Timer 2 Interrupt 4(1) ES0 R,W Enable UART0 Interrupt 3(1) ET1 R,W Enable Timer 1 Interrupt 2(1) EX1 R,W Enable External Interrupt INT1 1(1) ET0 R,W Enable Timer 0 Interrupt 0(1) EX0 R,W Enable External Interrupt INT0 |
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