PIC16F627A datasheet(109/180 Pages) MICROCHIP

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DS40044D-page 107

PIC16F627A/628A/648A

14.5

Interrupts

The PIC16F627A/628A/648A has 10 sources of

interrupt:

• External Interrupt RB0/INT

• TMR0 Overflow Interrupt

• PORTB Change Interrupts (pins RB<7:4>)

• Comparator Interrupt

• USART Interrupt TX

• USART Interrupt RX

• CCP Interrupt

• TMR1 Overflow Interrupt

• TMR2 Match Interrupt

• Data EEPROM Interrupt

The Interrupt Control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on Reset.

The “return-from-interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which re-

enables RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag is contained in the special

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine, the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid RB0/

INT recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 14-15).

The latency is the same for one or two-cycle instructions.

Once in the interrupt service routine, the source(s) of the

interrupt can be determined by polling the interrupt flag

bits. The interrupt flag bit(s) must be cleared in software

before re-enabling interrupts to avoid multiple interrupt

requests.

FIGURE 14-14:

INTERRUPT LOGIC

Note 1: Individual interrupt flag bits are set

regardless

the

status

their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

TMR2IF

TMR2IE

CCP1IF

CCP1IE

CMIF

CMIE

TXIF

TXIE

RCIF

RCIE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (if in Sleep mode)(1)

Interrupt to CPU

EEIE

EEIF

TMR1IF

TMR1IE

Note 1: Some peripherals depend upon the system clock for operation. Since the system clock is

suspended during Sleep, only those peripherals which do not depend upon the system

clock will wake the part from Sleep. See Section 14.8.1 “Wake-up from Sleep”.

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