PIC16F627A datasheet(51/180 Pages) MICROCHIP

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DS40044D-page 49

PIC16F627A/628A/648A

7.1

Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

7.2

Timer1 Operation in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode, the TMR1 register pair value increments on

every rising edge of clock input on pin RB7/T1OSI/PGD

when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/

PGC when bit T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple-counter.

In this configuration, during Sleep mode, the TMR1

external clock is present, since the synchronization

circuit is shut off. The prescaler however will continue

to increment.

7.2.1

EXTERNAL CLOCK INPUT TIMING

FOR SYNCHRONIZED COUNTER

MODE

When an external clock input is used for Timer1 in

Synchronized Counter mode, it must meet certain

requirements. The external clock requirement is due to

internal phase clock (TOSC) synchronization. Also,

there is a delay in the actual incrementing of the TMR1

When the prescaler is 1:1, the external clock input is

the same as the prescaler output. The synchronization

of T1CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2 TOSC (and

a small RC delay of 20 ns) and low for at least 2 TOSC

(and a small RC delay of 20 ns). Refer to Table 17-8 in

the Electrical Specifications Section, timing parameters

45, 46 and 47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous ripple-counter

type prescaler so that the prescaler output is symmetri-

cal. In order for the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T1CKI to have a

period of at least 4 TOSC (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement on

T1CKI high and low time is that they do not violate the

minimum pulse width requirements of 10 ns). Refer to

the appropriate electrical specifications in Table 17-8,

parameters 45, 46 and 47.

FIGURE 7-1:

TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

Note

When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set flag bit

TMR1IF on

Overflow

TMR1

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