PIC16F627A datasheet(79/180 Pages) MICROCHIP

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DS40044D-page 77

PIC16F627A/628A/648A

12.2

USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one Start bit, eight or nine data bits

and one Stop bit). The most common data format is

8-bit. A dedicated 8-bit baud rate generator is used to

derive baud rate frequencies from the oscillator. The

USART transmits and receives the LSb first. The

USART’s transmitter and receiver are functionally

independent, but use the same data format and baud

rate. The baud rate generator produces a clock either

x16 or x64 of the bit shift rate, depending on bit BRGH

(TXSTA<2>). Parity is not supported by the hardware,

but can be implemented in software (and stored as the

ninth data bit). Asynchronous mode is stopped during

Sleep.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

12.2.1

USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 12-1. The heart of the transmitter is the Transmit

(serial) Shift Register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the Stop bit has been

transmitted from the previous load. As soon as the Stop

bit is transmitted, the TSR is loaded with new data from

the TXREG register (if available). Once the TXREG

in one TCY), the TXREG register is empty and flag bit

TXIF (PIR1<4>) is set. This interrupt can be enabled/

disabled

setting/clearing

enable

bit

TXIE

( PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in

software. It will reset only when new data is loaded into

the TXREG register. While flag bit TXIF indicated the

status of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register.

Status bit TRMT is a read-only bit which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the Baud Rate Generator (BRG) has produced a

shift clock (Figure 12-1). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally when transmission

is first started, the TSR register is empty, so a transfer

to the TXREG register will result in an immediate

transfer to TSR resulting in an empty TXREG. A back-

to-back transfer is thus possible (Figure 12-3). Clearing

enable bit TXEN during a transmission will cause the

transmission to be aborted and will reset the

transmitter. As a result the RB2/TX/CK pin will revert to

high-impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG

to the TSR register (if the TSR is empty). In such a

case, an incorrect ninth data bit may be loaded in the

TSR register.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

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