PIC16F627A datasheet(30/180 Pages) MICROCHIP

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PIC16F627A/628A/648A

DS40044D-page 28

4.3

PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 4-4 shows the

two situations for loading the PC. The upper example

in Figure 4-4 shows how the PC is loaded on a write to

PCL (PCLATH<4:0>

→ PCH). The lower example in

Figure 4-4 shows how the PC is loaded during a CALL

or GOTO instruction (PCLATH<4:3>

→ PCH).

FIGURE 4-4:

LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556 “Implementing a Table Read”

(DS00556).

4.3.2

STACK

The PIC16F627A/628A/648A family has an 8-level

deep x 13-bit wide hardware stack (Figure 4-1). The

stack space is not part of either program or data space

and the Stack Pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a RETURN,

RETLW

or a

RETFIE

instruction execution. PCLATH is not affected

by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

4.4

Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no-operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 4-5.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

EXAMPLE 4-1:

INDIRECT ADDRESSING

PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL,

RETURN,

RETLW

and RETFIE

instructions, or the vectoring to an

interrupt address.

MOVLW

0x20

;initialize pointer

MOVWF

FSR

;to RAM

CLRF

INDF

;clear INDF register

INCF

FSR

;inc pointer

BTFSS

FSR,4

;all done?

GOTO

;no clear next

;yes continue

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