PIC16F627A datasheet(70/180 Pages) MICROCHIP

70 / 180 page

PIC16F627A/628A/648A

DS40044D-page 68

FIGURE 11-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

EXAMPLE 11-1:

VOLTAGE REFERENCE

CONFIGURATION

11.2

Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 11-1) keep VREF from approaching VSS or VDD.

The Voltage Reference module is VDD derived and

therefore, the VREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Voltage Ref-

erence module can be found in Table 17-3.

11.3

Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time out, the contents of

the VRCON register are not affected. To minimize

current consumption in Sleep mode, the Voltage

Reference module should be disabled.

11.4

Effects of a Reset

A device Reset disables the Voltage Reference module

by clearing bit VREN (VRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The VREF

value select bits, VRCON<3:0>, are also cleared.

11.5

Connection Considerations

The Voltage Reference module operates independently

of the Comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and the VROE bit, VRCON<6>, is

set. Enabling the Voltage Reference module output onto

the RA2 pin with an input signal present will increase

current consumption. Connecting RA2 as a digital output

with VREF enabled will also increase current consump-

tion.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

Voltage Reference module output for external connec-

tions to VREF. Figure 11-2 shows an example buffering

technique.

Note:

R is defined in Table 17-3.

VRR

VR3

VR0

(From VRCON<3:0>)

16-1 Analog Mux

VREN

VREF

16 Stages

VDD

VSS

MOVLW

0x02

;4 Inputs Muxed

MOVWF

CMCON

;to 2 comps.

BSF

STATUS,RP0 ;go to Bank 1

MOVLW

0x07

;RA3-RA0 are

MOVWF

TRISA

;outputs

MOVLW

0xA6

;enable VREF

MOVWF

VRCON

;low range set VR<3:0>=6

BCF

STATUS,RP0 ;go to Bank 0

CALL

DELAY10

;10

μs delay

PIC16F627A датащи(PDF) 70 Page - Microchip Technology

PIC16F627A датащи(HTML) 70 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL